演講/活動
2019-02-13 09:29:07陳秋雲(2019.3.7)#Topic : Design for Reliability in the Nano-CMOS Era and how Negative Capacitance...
#Topic : Design for Reliability in the Nano-CMOS Era and how Negative Capacitance Transistor can address the Fundamental Limitations in Technology Scaling
#WELCOME ALL TO COME →
#Time : March 7, 2019 Thursday 10:30AM—12:00PM
#Venue : R108,1F Engineering Building 4, NCTU
交通大學工程四館一樓知新廳(108室)
#Speaker : Dr. Hussam Amrouch
Research Group Leader and the Chair for Embedded Systems (CES), Karlsruhe Institute of Technology (KIT), Germany
#Host : Prof. Hung-Ming Chen 陳宏明 / Director, Inst. of Electronics, NCTU
#Abstract : The inability of MOSFET transistors to switch faster than 60mV/decade, due to the nonscalable Boltzmann factor, is the key fundamental limit in physics for technology scaling. This is, in fact, the bottleneck in voltage scaling, which has led to the discontinuation of Dennard’s scaling. As a result, on-chip power densities have continuously increased and the operating frequency of processors stopped improving in the last decade to prevent unsustainable on-chip temperatures. In addition, technology scaling is reaching limits in which displacing few atoms within transistors, due to aging phenomena, provokes uncertainty in the electrical characteristics of MOSFETs leading to catastrophic errors during operation. Thus, the customary trend in which performance is gained with technology scaling will soon become profound, if not impossible, due to the inevitable need to include wider and wider timing guardbands to ensure reliability.
In the first part of this talk, we will demonstrate how reliability degradations can be investigated from physics all the way to the system level. We will show how we can bring aging-awareness to existing commercial EDA tool flows based on degradation-aware cell libraries that allow designers to accurately estimate guardbands as well as efficiently contain them. We will also demonstrate how nondeterministic aging-induced timing errors can be converted into deterministic and controlled approximations instead.
In the second part of this talk, we explain how Negative Capacitance FET (NCFET), which is an emerging technology that suppresses the fundamental limit of sub-threshold swing and pushes it to below 60mV/decade, can revive the prior trends in processor design with respect to voltage and frequency scaling. We will focus on answering the following three questions to draw the impact of NCFET technology on computing efficiency: In how far NCFET technology will enable processors (i) to operate at higher frequencies without increasing voltage, (ii) to operate at higher frequencies without increasing power density, and (iii) to operate at lower voltages, while still fulfilling performance requirements -- which is substantial for IoT devices, where available power budgets are extremely restricted.
#WELCOME ALL TO COME →
#Time : March 7, 2019 Thursday 10:30AM—12:00PM
#Venue : R108,1F Engineering Building 4, NCTU
交通大學工程四館一樓知新廳(108室)
#Speaker : Dr. Hussam Amrouch
Research Group Leader and the Chair for Embedded Systems (CES), Karlsruhe Institute of Technology (KIT), Germany
#Host : Prof. Hung-Ming Chen 陳宏明 / Director, Inst. of Electronics, NCTU
#Abstract : The inability of MOSFET transistors to switch faster than 60mV/decade, due to the nonscalable Boltzmann factor, is the key fundamental limit in physics for technology scaling. This is, in fact, the bottleneck in voltage scaling, which has led to the discontinuation of Dennard’s scaling. As a result, on-chip power densities have continuously increased and the operating frequency of processors stopped improving in the last decade to prevent unsustainable on-chip temperatures. In addition, technology scaling is reaching limits in which displacing few atoms within transistors, due to aging phenomena, provokes uncertainty in the electrical characteristics of MOSFETs leading to catastrophic errors during operation. Thus, the customary trend in which performance is gained with technology scaling will soon become profound, if not impossible, due to the inevitable need to include wider and wider timing guardbands to ensure reliability.
In the first part of this talk, we will demonstrate how reliability degradations can be investigated from physics all the way to the system level. We will show how we can bring aging-awareness to existing commercial EDA tool flows based on degradation-aware cell libraries that allow designers to accurately estimate guardbands as well as efficiently contain them. We will also demonstrate how nondeterministic aging-induced timing errors can be converted into deterministic and controlled approximations instead.
In the second part of this talk, we explain how Negative Capacitance FET (NCFET), which is an emerging technology that suppresses the fundamental limit of sub-threshold swing and pushes it to below 60mV/decade, can revive the prior trends in processor design with respect to voltage and frequency scaling. We will focus on answering the following three questions to draw the impact of NCFET technology on computing efficiency: In how far NCFET technology will enable processors (i) to operate at higher frequencies without increasing voltage, (ii) to operate at higher frequencies without increasing power density, and (iii) to operate at lower voltages, while still fulfilling performance requirements -- which is substantial for IoT devices, where available power budgets are extremely restricted.
