演講/活動
2019-03-06 13:02:56陳秋雲(2019.4.22)#Talk Ultra-Low-Power Computing Hardware Design in the Era of AI and ML
#Talk Ultra-Low-Power Computing Hardware Design in the Era of AI and ML
#Welcome all to come ～～～
#Time
April 22, 2019 ( Monday 10:00AM—12:00PM )
#Venue
R108,1F Engineering Building 4, NCTU
交通大學工程四館一樓知新廳(108室)
#Speaker
Dr. Mingoo Seok / Associate Professor
Dept. of Electrical Engineering, Columbia University
#Host
Dr. Po-Hung Chen / Associate Professor
Institute of Electronics, NCTU
#Language
English
#Abstract
Computing technology has been the backbone of our society. Its importance is hard to overemphasize. Today, we again confirm its extreme importance with recent advances in artificial intelligence and deep learning. Those emerging workloads impose an unprecedented amount of arithmetic complexity and data access beyond our existing computing systems can barely handle. Across the computing systems from data centers, to mobile, and to extreme implants will face a major challenge in achieving desirable speed, energy-efficiency, and accuracy for truly enabling intelligent systems. In this seminar, we will outline the important bottlenecks to designing ultra-low-power computing hardware for AI and ML workloads, notably the end of Moore’s Law and the memory wall problem. We will then discuss several approaches that our group has been working on, including in-memory computing, hybrid analog-digital computing, and digital multi-core accelerator, and nanowatt DVS hardware. We will introduce several test-chip prototypes and their measurement results.
#Welcome all to come ～～～
#Time
April 22, 2019 ( Monday 10:00AM—12:00PM )
#Venue
R108,1F Engineering Building 4, NCTU
交通大學工程四館一樓知新廳(108室)
#Speaker
Dr. Mingoo Seok / Associate Professor
Dept. of Electrical Engineering, Columbia University
#Host
Dr. Po-Hung Chen / Associate Professor
Institute of Electronics, NCTU
#Language
English
#Abstract
Computing technology has been the backbone of our society. Its importance is hard to overemphasize. Today, we again confirm its extreme importance with recent advances in artificial intelligence and deep learning. Those emerging workloads impose an unprecedented amount of arithmetic complexity and data access beyond our existing computing systems can barely handle. Across the computing systems from data centers, to mobile, and to extreme implants will face a major challenge in achieving desirable speed, energy-efficiency, and accuracy for truly enabling intelligent systems. In this seminar, we will outline the important bottlenecks to designing ultra-low-power computing hardware for AI and ML workloads, notably the end of Moore’s Law and the memory wall problem. We will then discuss several approaches that our group has been working on, including in-memory computing, hybrid analog-digital computing, and digital multi-core accelerator, and nanowatt DVS hardware. We will introduce several test-chip prototypes and their measurement results.
