系所成員

 

地址:新竹市大學路1001號工程四館 501室
TEL:(03)573-1830
Email:schung@nycu.edu.tw

實驗室: 工程四館 411室 03-5712121 分機 54224

(mailing address)
Department of Electrical Eng. and Institute of Electronics
National Yang Ming Chiao Tung University (NYCU)
1001 University Road, Hsinchu 300
Taiwan
Tel: 886-3-573 1830

個人網頁

實驗室網頁或詳細履歷

前瞻元件與技術實驗室(Emerging Device and Technology Lab)

學經歷

學歷 (Education)

• 美國伊利諾大學香檳校區電機工程博士 (Ph.D. University of Illinois at Urbana-Champaign), 1985.

現職 (Current Position)

• 交通大學講座教授 NCTU Chair Professor/聯華電子研究講座教授 UMC Research Chair Professor

經歷 (Working Experience)

• IEEE VLSI-TSA, Executive Committee member (2022~)
• IEEE Fellow Committee, member (2022~)
• IEEE Silicon Nanoelectronics Workshop (SNW), General Chair (2022)
• IEEE Symposium on VLSI Technology and Circuits, Executive Committee member (2020~)
• Applied Physics A (Springer), Senior Editor (2020~)
• IEEE Silicon Nanoelectronics Workshop (SNW), General Chair (2018)
• IEEE Life Fellow (2018)
• Research of Excellence Program, Ministry of Science and Technology, PI 科技部自由型卓越學研計畫 總主持人, (2017~2019)
• Applied Physics A (Springer), Editor (2017~2019)
• IEEE EDS 50th WIMNACT workshop Chair, EDS Adcom mid-year meeting, May 2, 2016
• IEEE IPFA Conference, General Chair, 2015
• IEEE VLSI Technology and Circuits Committee, Focus Session Chair, 2014- 2015
• IEEE EDS Elected Board of Governor (IEEE美國總會電子元件學會執行委員) (2012-2017)
• IEEE EDS, Education Committee, Member, 2015-2018
• IEEE Journal of EDS, Editor (2015~2019)
• IEEE EDS Regions/Chapters-Asia Pacific, Chair (2013-2014)
• International Solid State Devices and Materials Symposium (SSDM), JSAP, Organizing Committee member, (2010~)
• 美國加州大學Merced分校客座教授 Visiting Professor, UC-Merced (2009.2- 2010.2)
• 美國Stanford客座, 研究所授課Visiting Professor,Guest Instructor (graduate course) (2009 Fall)
• 交通大學國際長 Dean, Office of International Affairs (2007/9/20- 2008/7/31)
• 交通大學頂尖大學計畫執行長 Executive Director, NCTU Top-University Plan (2007/2/1~ 2007/9/20)
• 交通大學講座教授 NCTU Chair Professor (2006.2 ~)
• IEEE Fellow 國際電機電子工程師學會會士(2006)
• 聯華電子研究講座教授 UMC Research Chair Professor (2005 ~)
• 電機資訊學院學士(菁英)班主任 Department Head, EECS Undergraduate Honors Program (2004-2005)
• 美國史丹佛大學訪問學者 Visiting Scholar, Stanford University (2001-2002)
• 交大電子工程系教授 Full Professor, NCTU (1989 ~ 2006)
• 交大電子工程系副教授 Associate Professor, NCTU (1987-1989)
• IEEE EDS Ex-Officio Member
• IEEE EDS Elected AdCom Member (IEEE美國總會電子元件學會執行委員) (連任 2007-2009)
• IEEE Taipei Section Board Member (IEEE 台北分會理事), (連任 2007 ~ 2008)
• IEEE Taipei Section Board Member (IEEE 台北分會理事), (2005 ~ 2006)
• SSDM(International Solid State Devices and Materials Symposium), Technical Program Vice-Chair, 2007-2009
• IEEE 6th WIMNACT Workshop Chair (2005)
• IEEE EDS Graduate Student Fellowship Committee Member (2005 ~)
• IEEE EDS Elected AdCom Member (IEEE美國總會電子元件學會執行委員) (2004-2006)
• IEEE EDS Regions/Chapters-AP Vice Chair (IEEE EDS總會亞太區域分會副主席) (2004 ~)
• IEEE ICMTS conference, TPC Member (2005-2007)
• IEEE VLSI Technology and Circuit Committee, member (2004 ~)
• EDMS(Electron Devices and Materials Symposium), Technical Program Chair (2004)
• Guest Editor, IEEE TDMR Journal (2004)
• IEEE SMTW, workshop Technical Program, Co-Chiar (2004)
• IEEE IPFA Technical Program Chair (2004)
• IEEE VLSI-TSA, Taiwan-Committee Chair (2003)
• IEEE Distinguished Lecturer (2002 ~)
• IEEE EDL Editor (2002 ~ 2008)
• IEEE EDS Taipei Chapter Chair (EDS台北分會長) (2000 ~2010))
• IEEE IEDM Committee Member, Session Chair (2003-2004)
• IEEE IRPS Committee Member, Session Chair (2003-2004)
• IEEE Symposium on VLSI Technology, Committee Member, session Chair (2000 ~)
• 台積電公司 計劃顧問 TSMC Consultant (1993- 1999)
• 茂矽電子公司計劃顧問 MOSEL Consultant (1992)
• 美國伊利諾大學固態電子實驗室研究助理 Reseach Assistant,
• Illinois Solid State Electronics Lab- Prof. C. T. Sah (CMOS發明人) group (1983-1985)

研究方向

• 先進CMOS元件技術及可靠性
• 電阻式記憶體元件與電路
• AI及網路安全晶片

簡介

簡歷 (Bios)

        Steve S. Chung received his Ph.D. degree from the University of Illinois at Urbana-Champaign, in Electrical Engineering in 1985. His Ph.D.thesis advisor is the world-famous scholar and CMOS Co-Inventor, Prof. C. T. Sah.

        Currently, he is an NYCU(NCTU) Chair Professor, UMC Research Chair Professor at the National Chiao Tung University (NCTU), where he worked as Dean of International Affairs,between 2007-2008. Between 2004-2005, he was the first Department Head of EECS Honors Program, to promote a new undergraduate program for academic excellence, at NCTU where he has served since 1987. He was a Visiting Professor with the University of California-Merced(2009-2010), a guest Instructor at Stanford (2009) and also a visiting scholar to Stanford University, CA, in 2001. He was also the consultant to both TSMC and UMC on developing CMOS and flash memory technologies. His current research areas include CMOS device technology with emphasis on trigate and Tunneling FET, flash memory technology, resistance memory technology,embedded memory technology, reliability characterization and modeling. He has published more than 300 journal and conference papers, one textbook, and holds more than 40 patents. Since 1995, he has personally presented more than 35 times in the world leading IEEE conferences, IEDM and VLSI, with focus on the reliability and technology of advanced-CMOS, flash memory, resistance memory etc. In particular, he is the first (from Taiwan) to present the paper at VLSI Technology symposium in 1995. Three highest impact inventions (with both paper publishing and patents) by his team includes: (1) IFCP(Incremental Frequency Charge Pumping)[1], a milestone for the CMOS reliability analysis beyond the 90nm generation. This method can replace the conventional CV method (which has been used for 50 years) in measuring the interface/oxide traps with small dimensions and with gate oxide thickness in the tunneling regime. (2) A unique Ig-RTN transient measurement on the understanding of FET breakdown based on the characterization of traps in the gate dielectric. A third breakdown was discovered [2], different from the well known soft-breakdown and hard-breakdown. This led to the invention of an OTP structure [3] with vast economic benefit. (3) A new invention of one-transistor nonvolatile memory [4] which will be able to replace conventional Floating Gate since its inception in 1967, as floating gate reaches its scaling limit at around 20nm. These are cornerstones for a sustainable semiconductor industry when the Silicon technology scaling is continuing.

        
        He is an IEEE Fellow, IEEE EDS BoG(Board Governor) member (2014-2016), EDS AdCom member (2004-2009), IEEE Distinguished Lecturer, EDS Regions/Chapters Vice-Chair/Chair, and Editor of J-EDS (2014-), Editor of EDL(2002-2008). He has served on the committees of premiere conferences, e.g., VLSI Technology, IEDM, IRPS, etc. Also, he has been the Technical Program Chair of 2004 and 2015 IPFA, the Technical Program Vice-Chair of SSDM (the largest conference in semiconductor areas in Japan). ED Taipei chapter was awarded the 2002 EDS Chapter of the Year Award under his leadership as the chapter chair. This is a remarkable achievement and milestone to the IEEE societies in Taiwan since the chapter is the first one to receive this honor among those 26 IEEE Taipei chapters at that time. He was awarded 3 times outstanding Research Award for excellence in research, as well as the top-PI in 2003, and the current distinguished NSC Research Fellow, from the National Science Council. He was also granted Distinguished EE Professor and Engineering Professor by the Engineering Societies of Taiwan.
        
        He was the recipient of 2013 Pan Wen Yuan award in recognizing his outstanding achievements in the semiconductor research.    

[1] S.S. Chung; S.-J. Chen; C.-K. Yang; S.-M. Cheng et al., “A novel and direct determination of the interface traps in sub-100 nm CMOS devices with direct tunneling regime (12~16 A) gate oxide,” Symp. VLSI Tech., 2002. DOI: 10.1109/VLSIT.2002.1015394
[2] S. S. Chung, “The discovery of a third breakdown: phenomenon, characterization and applications,” Applied Physics-A, Jan. 17, 2023
https://doi.org/10.1007/s00339-023-06383-w
[3] S. S. Chung et al., Dielectric Fuse Memory Circuit and Operation Method Thereof, US patent No. 10,127,993,
November 13, 2018.
[4] S. S. Chung, E. R. Hsieh, S. P. Yang, and C. H. Chuang, “ A Novel One-Transistor Resistance-Gate Nonvolatile
Memory,” 74th Device Research Conference, Delaware, pp. 251-252, June 19-22, 2016.

各項榮譽與重要貢獻 (Honors/Awards & Major Achievements)

       
[5] W. Y. Yang, B. Y. Chen, C. C. Chuang, E. R. Hsieh, K. S. Li, and S. S. Chung, “Novel Concept of Hardware Security in Using
Gate-switching FinFET Nonvolatile Memory to Implement True-Random-Number Generator,” in IEDM Tech. Dig., San Francisco CA, Dec. 12-16, 2020.
(see report in Nature Electronics, by C. Varnava, FinFETS for Cryptography, Dec. 11, 2020, https://www.nature.com/articles/s41928-020-00521-5
[6] E. R. Hsieh, S. S. Chung et al., “First Demonstration of Flash RRAM on Pure CMOS Logic 14nm FinFET Platform Featuring Excellent Immunity to Sneak-path and MLC Capability,” in Symposium on VLSI Technology, pp. 64-65, Kyoto, June 13-17, 2017. A world first FinFET Resistance NVM feasible for embedded memory in advance 14nm platform (A highlight paper)

專利(patents): > 40
論文發表(published paper): IEEE Journal and Conference Papers (more than 300)  

IEDM/VLSI論文發表: (First author發表) ~35篇 (up to 2022.12)
1995 VLSI Technology 台灣首次上榜論文為本研究群發表 (The first paper contributed from Taiwan)
1997 VLSI Technology 台灣唯一上榜論文為本研究群發表 (The only paper contributed from Taiwan) [7]
1995-2016 VLSI Technology 台灣各大學上榜論文統計, 37% 為本研究群發表 (第一作者)
        
2002 IEEE EDS Chapter of the Year Award 為莊教授擔任IEEE EDS Taipei Chapter會長期間, 50年來台灣地區分會第一次獲得榮譽 (台灣現有26個IEEE 分會)
        
IEDMS Best Paper Award (最佳論文獎) (1996)
IEDMS Best Paper Award (最佳論文獎) (2010)
        
[1] S. S. Chung et al., in Symposium on VLSI Tech., pp. 74-75, Hawaii, 2002. ( also, US patent, No. 6,746,883)
[7] S. S. Chung et al., in Symposium on VLSI Tech., pp. 111-112, Kyoto, 1997.

        
Citations:
Who’s who in the world, 1999, 2000, 2001 Editions
Who’s who in finance, 2000 Edition
Who’s who in Asia, 2006 Edition